FIG. 1 shows a block diagram of a display device 100 according to the prior art. The display device 100 includes a display panel 102 such as a LCD (liquid crystal display) panel, a LSI (liquid crystal display system interface) 104, and a printed circuit board 106. The printed circuit board 106 includes circuit components such as a plurality of external capacitors 108, 109, 110, 111, and 112 coupled to the LSI 104. Such external capacitors 108, 109, 110, 111, and 112 for example are external capacitors Cext1, Cext2, Cext3, Cext4, and Cext5 to be described later herein.
FIG. 2 shows a circuit diagram of an example pixel 120 of the LCD panel 102 of FIG. 1 as known in the prior art. A first capacitor Clc represents a liquid crystal formed for the pixel 120, and a second capacitor Cst is a storage capacitor formed for storing charge when biasing the liquid crystal Clc. A thin film transistor M1 is formed with a source S coupled to first terminals of the capacitors Clc and Cst having second terminals with a common voltage VCOM applied thereon.
The thin film transistor M1 also includes a gate G with a gate signal Vg applied thereon, and a drain D with a drain signal Vd applied thereon. FIG. 2 also shows a gate-to-drain parasitic capacitance Cgd between the gate G and the drain D of the thin film transistor M1. FIG. 2 further shows a gate-to-source parasitic capacitance Cgs between the gate G and the source S of the thin film transistor M1.
FIG. 3 shows a timing diagram of signals during operation of the example pixel 120 of FIG. 2 having undesired kickback voltages. Referring to FIGS. 2 and 3, the drain signal Vd is activated to an active high voltage before time point T1. At time point T1, the gate signal Vg is activated to an active high voltage until time point T2. Between time points T1 and T2, a pixel voltage Vp at the source of the thin film transistor M1 rises to a higher voltage V1 since the drain signal Vd is at the activated high voltage.
At time point T2 when the gate signal Vg drops to a low voltage, the pixel voltage Vp drops by a first kickback voltage Vkb1 which is expressed as follows:Vkb1=Vgp×Cgd/(Clc+Cst+Cgd)Vgp above is a total drop in voltage in the gate signal Vg at time point T2. After time point T2, the pixel voltage Vp further decreases according to an RC circuit illustrated in FIG. 4 with Roff being the off-resistance of the thin film transistor M1 and Ct=(Clc+Cst).
Further referring to FIGS. 2 and 3, the gate signal Vg is activated again to the active high voltage at time point T3 until time point T4. Between time points T3 and T4, the pixel voltage Vp decreases to a low voltage V2 since the drain signal Vd is deactivated to a lower voltage. At time point T4 when the gate signal Vg drops to the low voltage, the pixel voltage Vp drops by a second kickback voltage Vkb2 which is expressed as follows:Vkb2=Vgp×Cgd/(Clc+Cst+Cgd)After time point T4, the pixel voltage Vp increases according to the RC circuit of FIG. 4.
Such kickback voltages Vkb1 and Vkb2 undesirably cause flickering on the LCD panel 102. Thus, a mechanism for minimizing flickering on the LCD panel 102 from such kickback voltages Vkb1 and Vkb2 is desired.